1. Field of the Invention
Embodiments of the present invention generally relate to a method and apparatus for planarizing a substrate by electropolishing techniques.
2. Description of the Related Art
Reliably producing sub-micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
Currently, copper and its alloys have become the metals of choice for sub-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 μΩ-cm compared to 3.1 μΩ-cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
FIG. 1 is a schematic cross-sectional view of one embodiment of a substrate structure 100 at one stage in the formation of a copper interconnect. Depending on the processing stage, the substrate structure 100 comprises a substrate 110, such as a semiconductor substrate or a glass substrate, and may include other materials formed over the substrate, such as a dielectric layer, conductive layer, and/or other layers. A dielectric layer 112, such as a silicon dioxide layer or a low-k dielectric layer, may be formed over the substrate 110. One example of a low-k dielectric layer is an oxidized organosilane layer or an oxidized organosiloxane layer described in more detail in commonly assigned U.S. Pat. No. 6,348,725, issued Feb. 19, 2002, which is incorporated by reference herein. The dielectric layer 112 may be patterned and etched to form apertures 114. A conductive layer 116, such as a copper seed layer and an electroplated copper bulk layer, may be deposited over the dielectric layer 112 to fill the apertures 114. A barrier layer (not shown), such as tantalum and/or tantalum nitride layer, may be formed between the dielectric layer 112 and the conductive layer 116.
As layers of materials are sequentially formed, the upper most surface of the substrate structure 100 may become non-planar. For example, the upper surface may comprise peaks 120 (or protuberances) and valleys 122 (or recesses). The difference in the height of a peak 120 and a valley 122 is called the step height 130. For example, the step height may be about 5,000 Å for a conductive layer 116 deposited to a thickness 140 of about 10,000 Å. A non-planar substrate surface may require planarization prior to further processing.
Planarizing or polishing a substrate surface is a process intended to remove material from the substrate surface to form a more planar substrate surface. Planarization is also useful in removing excess deposited material used to fill the features and in removing undesired surface topography, such as surface defects, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical polishing (CMP) is one technique being used to remove conductive material from the substrate surface. Chemical mechanical polishing comprises contacting and moving a substrate surface relative to a polishing pad having a slurry or other fluid medium to remove material by chemical and mechanical forces. One problem with CMP techniques is that the down force used to contact the substrate structure and the polishing pad may affect the mechanical integrity of low-k dielectric materials formed on the substrate, which are generally porous and relatively soft. Another problem with CMP techniques is the long process time for removal of copper.
Electropolishing is another technique being explored to remove conductive material from a substrate surface. Electropolishing techniques comprise applying an anodic bias to the substrate surface to remove conductive material, such as copper, by an ion dissolution mechanism. One problem with conventional electropolishing techniques is that the step height is not sufficiently decreased before a portion of the conductive layer 116 is removed down to the dielectric layer 112 or without causing dishing of the copper filling the apertures 114. As a consequence, electropolishing a non-planar substrate surface having peaks 120 and valleys 122 does not substantially decrease the step height 130 between the peaks 120 and valleys 122.
Therefore, there is a need for an improved method and apparatus for removing conductive material from a substrate surface.